1. Field of the Invention
The invention relates to design of semiconductor chips. More specifically, the invention relates to a method and an apparatus for minimizing sub-threshold leakage current for logic circuits in sleep mode.
2. Related Art
Increasing circuit density is an important component for lowering the cost and increasing the performance of semiconductor chips. Therefore, device sizes in semiconductor chips have been steadily shrinking. However, as devices become smaller, sub-threshold leakage current becomes an increasingly larger part of the overall power consumption of the semiconductor chips. For example, in semiconductor chips with a devices size of 45 nm, sub threshold leakage accounts for approximately 50 percent of the total power consumed.
Sub-threshold leakage current occurs when the gate voltage is below the threshold voltage of a transistor. Thus, sub-threshold leakage occurs when the device is turned off because the gate voltage is below the threshold voltage. Implementing a sleep mode for logic blocks not currently in use can reduce sub-threshold leakage currents. FIG. 1 is a block diagram of a circuit using multi-threshold CMOS (MTCMOS) to implement sleep mode in a logic block. Specifically, a logic block 120 coupled to the positive power supply through a high threshold P-type transistor 110, which provides a virtual positive power node V13 VDD for logic block 120. For clarity the voltage at the positive power supply is referred to as positive supply voltage VDD. Logic block 120 is coupled to ground through a high threshold N-type transistor 130, which provides a virtual ground node V_GND for logic block 120. For clarity, the voltage at ground is referred to as ground voltage VSS. A sleep signal SLEEP is applied to the gate of high threshold P-type transistor 110. Conversely, a not sleep signal !SLEEP (which is the inverse of sleep signal SLEEP) is applied to the gate terminal of high threshold N-type transistor 130. In normal operation, sleep signal SLEEP is at logic low and not sleep signal !SLEEP is at logic high. Therefore, both high threshold P-type transistor 110 and high threshold N-type transistor 130 are turned “on”. Consequently, the voltage at virtual positive power node V_VDD is very close to the positive supply voltage VDD and the voltage at virtual ground node V_GND is very close to ground voltage VSS. Therefore, logic block 120 can operate normally.
For sleep mode, sleep signal SLEEP is driven to logic high and not sleep signal !SLEEP is driven to logic low. Therefore, both high threshold P-type transistor 110 and high threshold N-type transistor 130 are turned “off”. This prevents normal operation of logic block 120 but also serves to reduce but not eliminate the sub-threshold leakage current in logic block 120 because the sub threshold leakage current is proportional to the drain to source voltage (VDS) of the transistors in logic block 120. Specifically, high threshold P-type transistor 110, logic block 120, and high threshold N-type transistor 130 act as a voltage divider ladder. Therefore, the voltage at virtual positive power node is slightly greater than the voltage at virtual ground node V_GND resulting in a small drain to source voltage for the transistors in logic block 120, which allows sub-threshold leakage currents in logic block 120.
Furthermore, storage elements in logic block 120 are not able to store state information (i.e., data) during sleep mode. To prevent loss of state information, redundant storage elements are used in logic block 120. The redundant storage elements are coupled directly to the positive power supply and ground rather than virtual positive power node V—VDD and virtual ground node V_GND. Thus, the redundant storage elements do not go into sleep mode. FIG. 2 shows an inverter 215 and an inverter 218 coupled together to form a storage element 210 from logic block 120. Thus, inverters 215 and 218 receive power from virtual positive power node V_VDD and virtual ground node V_GND. Therefore, when logic block 120 is put into sleep mode, storage element 210 loses the data in storage element 210 prior to entering sleep mode. To retain data during sleep mode, a redundant storage element 220 that is not put into sleep mode is used with each storage element 210. As illustrated in FIG. 2, an inverter 225 and an inverter 228 are coupled to form a redundant storage element 220. Redundant storage element 220 is coupled to storage element 210 through a pass gate 230. Redundant storage element 220 mirrors the data in storage element 210 during normal operation of logic block 120. However, unlike inverters 215 and 218, inverters 225 and 228 are powered directly from the positive power supply and ground. Therefore, when logic block 120 enters sleep mode, redundant storage element 220 stores the state of storage element 210 prior to entering sleep mode. When logic block 120 leaves sleep mode, redundant storage element 220 resets the data in storage element 210.
While redundant storage elements prevents loss of state information during sleep mode, the cost in terms of silicon resources for redundant storage elements is enormous. In addition to the area for the redundant storage elements, additional silicon area is used for routing the separate power lines to the redundant storage elements. Furthermore, the redundant storage elements consume additional power. Hence there is a need for method and system to reduce sub-threshold leakage currents with the ability to maintain state information.